Name
Abstract | ||
|---|---|---|
This paper proposes a parallel hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCSVT.2008.2004936 | Circuits and Systems for Video Technology, IEEE Transactions |
Keywords | Field | DocType |
SLAM (robots),embedded systems,feature extraction,field programmable gate arrays,microprocessor chips,mobile robots,parallel architectures,robot vision,system-on-chip,CMOS image sensor,Ethernet connection,PC-based implementation,SLAM,embedded processor,embedded robotics,field-programmable gate array,hardware optimizations,hardware-orientated optimizations,image feature detection,parallel hardware architecture,robotic control system on-a-chip,scale invariant feature transform algorithm,simultaneous localization and mapping,Embedded robotics,SIFT,SLAM,field-programmable gate array (FPGA) | Scale-invariant feature transform,Edge detection,Computer science,Real-time computing,Artificial intelligence,Simultaneous localization and mapping,Computer hardware,Computer vision,System on a chip,Field-programmable gate array,Feature extraction,Gate array,Hardware architecture | Journal |
Volume | Issue | ISSN |
18 | 12 | 1051-8215 |
Citations | PageRank | References |
76 | 4.25 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vanderlei Bonato | 1 | 145 | 17.19 |
| Eduardo Marques | 2 | 107 | 8.50 |
| Constantinides, G.A. | 3 | 76 | 4.25 |