Abstract | ||
---|---|---|
In macrocell based SoC design, a routing plan to decongest top channel is an important step during floor planning. While previous approaches attempt at reducing congestion of chip as a whole, there is no attempt to specifically decongest top channel. We present an algorithmic approach to decongest top channel by using very few feedthroughs. Results show that compared to conventional methods, we can decongest top channel by using 20% lesser feedthrough buffers, and better top channel routing resource utilization. |
Year | DOI | Venue |
---|---|---|
2009 | 10.1109/VLSI.Design.2009.83 | VLSI Design |
Keywords | Field | DocType |
VLSI,circuit layout,microprocessor chips,network routing,system-on-chip,feedthrough algorithm,floor planning,macrocell based SoC design,simultaneous routing,top channel routing resource utilization,Congestion,Feedthrough,Routing | System on a chip,Algorithm design,Network routing,Computer science,Computer network,Communication channel,Real-time computing,Electronic engineering,Chip,Very-large-scale integration,Feedthrough,Macrocell | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-0-7695-3506-7 | 0 |
PageRank | References | Authors |
0.34 | 4 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Shashank Prasad | 1 | 0 | 0.34 |
Anuj Kumar | 2 | 19 | 11.09 |