Name
Abstract | ||
|---|---|---|
Partial dynamic reconfiguration of FPGAs is a methodology that allows the efficient use of FPGAs resources and an improved degree of flexibility with respect to static hardware when designing an architecture on FPGA. Recently several tools, aiming at supporting the designer in the implementation and the validation processes involved in partial reconfiguration, have been released. Within this scenario we introduce a framework, called ReBit, intended to be complementary to the most important of tool suite available today, e.g. Xilinx ISE suite, improving the existing features and adding new ones, such as partial bit stream scheduling policy testing and algorithmic bus macros placement, using different APIs, integrated in the framework. These features have been validated using different Xilinx FPGAs Spartan 3, Virtex II Pro and Virtex 4. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/IPDPS.2011.145 | Parallel and Distributed Processing Workshops and Phd Forum |
Keywords | Field | DocType |
field programmable gate arrays,reconfigurable architectures,API,FPGA-based reconfigurable systems,ReBit,Virtex 4,Virtex II Pro,Xilinx FPGA Spartan 3,Xilinx ISE suite,algorithmic bus macros placement,field programmable gate array,partial bit stream scheduling policy testing,partial dynamic reconfiguration,tool suite,validation processes | Computer architecture,Suite,Computer science,Scheduling (computing),Field-programmable gate array,Virtex,Macro,Bitstream,Control reconfiguration,Embedded system,Reconfigurable computing | Conference |
ISSN | ISBN | Citations |
1530-2075 E-ISBN : 978-0-7695-4577-6 | 978-0-7695-4577-6 | 2 |
PageRank | References | Authors |
0.46 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Santambrogio, M.D. | 1 | 2 | 0.46 |
| Cazzaniga, A. | 2 | 19 | 2.46 |
| Bonetto, A. | 3 | 2 | 0.46 |
| D. Sciuto | 4 | 1720 | 176.61 |