Name
Abstract | ||
|---|---|---|
We show the advantage of quarternary decision diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISMVL.2009.35 | IEICE Transactions |
Keywords | Field | DocType |
decision diagrams,optimisation,logic function,optimization,quaternary decision diagram machine,BDD,MDD,PLC,code optimization,logic simulation,programmable logic controller | Program optimization,Boolean function,Data structure,Logic gate,Computer science,Arithmetic,Algorithm,Binary decision diagram,Electronic engineering,Influence diagram,Logic simulation,Programmable logic controller | Conference |
Volume | Issue | ISSN |
93-D | 8 | 0195-623X E-ISBN : 978-0-7695-3607-1 |
ISBN | Citations | PageRank |
978-0-7695-3607-1 | 6 | 0.56 |
References | Authors | |
21 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tsutomu Sasao | 1 | 1083 | 141.62 |
| Nakahara, H. | 2 | 6 | 0.56 |
| Matsuura, M. | 3 | 6 | 0.56 |
| Kawamura, Y. | 4 | 6 | 0.90 |