Title
Evaluating the training dynamics of a CMOS based synapse
Abstract
Recent work by the authors proposed compact low power synapses in hardware, based on the charge-coupling principle, that can be configured to yield a static or dynamic response. The focus of this work is to investigate the training dynamics of these synapses. Empirical models of the Post Synaptic Response (PSP), derived from hardware simulations, were developed and subsequently embedded into the MATLAB environment. A network of these synapses was then used to solve a benchmark problem using a well established training algorithm where the performance metric was convergence time, accuracy and weight range; the Spike Response Model (SRM) was used to implement point neurons. Results are presented and compared with standard synaptic responses.
Year
DOI
Venue
2011
10.1109/IJCNN.2011.6033355
Neural Networks
Keywords
Field
DocType
CMOS logic circuits,learning (artificial intelligence),neural nets,CMOS based synapse,MATLAB environment,SRM,charge-coupling principle,hardware simulations,post synaptic response,spike response model,training algorithm
Convergence (routing),Empirical modelling,Response model,Synapse,MATLAB,Computer science,Performance metric,CMOS,Artificial intelligence,Artificial neural network,Machine learning
Conference
ISSN
ISBN
Citations 
2161-4393
978-1-4244-9635-8
3
PageRank 
References 
Authors
0.43
19
4
Name
Order
Citations
PageRank
Ghani, A.130.77
McDaid, L.J.21045.22
A. Belatreche316512.40
Simon P. Kelly4569.89