Title
A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS
Abstract
A low-power, multimode polar transmitter based on a two-point injection PLL with a linearized VCO is implemented in 65-nm CMOS technology. A wideband feedback loop, nested inside the PLL with negligible area and power consumption overhead, linearizes and accurately controls the tuning characteristic of the VCO, which is a key requirement when directly modulating the oscillator. Differential delay between AM-PM paths is predictable and is self-calibrated. In WCDMA mode, the transmitter achieves 42/-58-dBc ACLR at 5/10-MHz offsets, -159-dBc/Hz receive band noise, and 2.9% EVM at 0-dBm output power while drawing 40-mA from a 3.6-V battery. The DG09 battery current is 25-mA based on a typical PA gain profile and the chip active area is 0.7-mm2.
Year
DOI
Venue
2011
10.1109/JSSC.2011.2166432
Solid-State Circuits, IEEE Journal of
Keywords
Field
DocType
3G mobile communication,CMOS integrated circuits,cellular radio,code division multiple access,low-power electronics,phase locked loops,radio transmitters,voltage-controlled oscillators,AM-PM paths,CMOS technology,DG09 battery current,PA gain profile,current 25 mA,differential delay,linearized VCO,low-power GSM-EDGE-WCDMA multimode polar transmitter,power 40 mW,power consumption overhead,size 65 nm,two-point injection PLL,voltage 3.6 V,wideband feedback loop,CMOS,VCO linearization,WCDMA,low-power,multimode,polar,transmitter,two-point injection PLL
Wideband,Transmitter,Phase-locked loop,Computer science,CMOS,Electronic engineering,Chip,Voltage-controlled oscillator,Feedback loop,Electrical engineering,Low-power electronics
Journal
Volume
Issue
ISSN
46
12
0018-9200
Citations 
PageRank 
References 
12
1.05
25
Authors
4
Name
Order
Citations
PageRank
Youssef, M.1121.05
Zolfaghari, A.2335.66
Mohammadi, B.3293.02
H. Darabi418559.95