Name
Abstract | ||
|---|---|---|
Power-efficiency results from several generations of I/O interfaces with specific goals are presented as well as the tradeoffs made within and across those designs. Foundational work in active-power reduction at a single rate for a symmetric system, the subsequent application of that work to a burst-mode asymmetric interface, and recent research on low-overhead bursting are discussed. Dynamic voltage frequency scaling and efficiency increases enabled by system level interconnect improvements are also considered as important techniques. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/CICC.2011.6055367 | Custom Integrated Circuits Conference |
Keywords | Field | DocType |
integrated circuit design,interface phenomena,microprocessor chips,I/O interfaces,active power reduction,burst mode asymmetric interface,dynamic voltage frequency scaling,high bandwidth applications,low overhead bursting,power efficient I/O design considerations,symmetric system | Dynamic voltage frequency scaling,Power efficient,Computer science,Input/output,Electronic engineering,Integrated circuit design,Interconnection,System level,High bandwidth | Conference |
ISSN | ISBN | Citations |
0886-5930 | 978-1-4577-0222-8 | 0 |
PageRank | References | Authors |
0.34 | 12 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eble, J.C. | 1 | 0 | 0.34 |
| Best, S. | 2 | 0 | 0.34 |
| Leibowitz, B. | 3 | 0 | 0.34 |
| Lei Luo | 4 | 56 | 12.41 |