Title
Reduced-complexity column-layered decoding and implementation for LDPC codes
Abstract
Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13%%m VLSI implementation technology. It is shown that a decoding throughput of nearly 4%Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.
Year
DOI
Venue
2011
10.1049/iet-com.2010.1002
Communications, IET
Keywords
Field
DocType
VLSI,codecs,computational complexity,parity check codes,LDPC codes,algorithmic transformation,computation complexity,judicious approximations,low density parity check decoder,reduced complexity column layered decoding,very large scale integration architectures
Concatenated error correction code,Sequential decoding,Computer science,Low-density parity-check code,Serial concatenated convolutional codes,Parallel computing,Decoding methods,List decoding,Very-large-scale integration,Clock rate
Journal
Volume
Issue
ISSN
5
15
1751-8628
Citations 
PageRank 
References 
18
1.08
10
Authors
3
Name
Order
Citations
PageRank
Zhiqiang Cui1181.08
Zhongfeng Wang2354.74
Xinmiao Zhang3181.08