Name
Abstract | ||
|---|---|---|
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and systematic increases in cache misses, degrading performance. In the worst case, these misses can effectively render the cache useless. These pathological cases, or "cache risk patterns'', are difficult to predict, test or debug, and their presence limits the usefulness of caches in safety critical real-time systems, especially in hard real-time environments. In this paper, we explore the effect of randomized cache replacement policies in real-time systems with stringent timing constrains. We present simulation-based results on representative examples that illustrate the problem of performance anomalies with standard cache replacement policies. We show that, by eliminating dependencies on access history, randomized replacement greatly reduces the risk of these cache-based performance anomalies, enabling probabilistic worst-case execution time analysis. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ECRTS.2009.30 | Dublin |
Keywords | Field | DocType |
cache storage,safety-critical software,cache risk patterns,cache-based performance anomalies,data access patterns,hardware caches,memory layout,probabilistic worst-case execution time analysis,randomized cache replacement policies,safety critical real-time systems | Cache invalidation,Cache pollution,Cache,Computer science,Real-time computing,Cache algorithms,Cache coloring,Bus sniffing,Probabilistic logic,Data access,Distributed computing | Conference |
ISSN | ISBN | Citations |
1068-3070 | 978-0-7695-3724-5 | 25 |
PageRank | References | Authors |
1.07 | 14 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. Quinones | 1 | 77 | 4.71 |
| Emery D. Berger | 2 | 1048 | 55.87 |
| Guillem Bernat | 3 | 1669 | 75.20 |
| Francisco J. Cazorla | 4 | 151 | 7.82 |