Name
Abstract | ||
|---|---|---|
This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful layout are adopted to obtain high-resolution in a low-supply. The ADC features 12-bit resolution, 100-MS/s sampling rate, differential nonlinearity (DNL) of ±0.58 LSB, integral nonlinearity (INL) of ±2.79 LSB, and power consumption of 30.4 mW. With a sampling frequency of a 100-MS/s and an input of a 2.4 MHz, the ADC achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 59.02 dB and 63.22 dB, at a supply voltage of 1.1 V, respectively. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISOCC.2011.6138617 | ISOCC |
Keywords | Field | DocType |
cmos integrated circuits,analogue-digital conversion,cmos technology,analog-to-digital converter,differential nonlinearity,frequency 2.4 mhz,integral nonlinearity,low-voltage circuit technique,pipelined adc,power 30.4 mw,power consumption,size 45 nm,voltage 1.1 v,word length 12 bit,adc,cmos,pipelined,spurious free dynamic range,sampling frequency,low voltage,high resolution | Integral nonlinearity,Dynamic range,Differential nonlinearity,Computer science,Sampling (signal processing),12-bit,Electronic engineering,Effective number of bits,CMOS,Successive approximation ADC,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4577-0710-0 | 1 | 0.54 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jae-Won Nam | 1 | 29 | 6.41 |
| Young-Deuk Jeon | 2 | 98 | 13.50 |
| seokju yun | 3 | 1 | 0.54 |
| Tae Moon Roh | 4 | 11 | 3.13 |
| Jong-Kee Kwon | 5 | 158 | 23.10 |