Paper Info
Title
Application specific processor for multi-standard video decoding
Abstract
Application-specific instruction processor is a new design methodology to develop optimized processors for specific applications. This paper proposes a new application-specific instruction processor and compiler for multi-standard video decoding. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for multi-standard video decoding, and compiler mapping techniques such as CKF(compiler known function) and inline assembly. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. Compared to the existing ARM processor, the proposed architecture and compiler result in about 20% improvement in video decoding in terms of total cycles as well as smaller hardware complexity.
Year
DOI
Venue
2011
10.1109/ISOCC.2011.6138625
ISOCC
Keywords
Field
DocType
data compression,video coding,6-stage pipelined dual issue vliw+simd architecture,arm processor,ckf,smic process,application-specific instruction processor,compiler known function,compiler mapping techniques,frequency 125 mhz,multistandard video decoding,size 130 nm,compiler,multimedia processor,video decoding,design methodology
ARM architecture,Computer architecture,Gate count,Computer science,Very long instruction word,Parallel computing,Inline assembler,Real-time computing,Compiler,Fujitsu FR,Decoding methods,Intrinsic function
Conference
ISBN
Citations 
PageRank 
978-1-4577-0710-0
8
1.55
References 
Authors
1
2
Name
Order
Citations
PageRank
Jae-Jin Lee1278.69
Nak-Woong Eum2319.55