Name
Abstract | ||
|---|---|---|
This paper describes a 60 GHz high gain power amplifiers (PA) designed in a 0.18-μm SiGe BiCMOS technology. It consists of four cascode stages with inter-stage matching implemented by the conductor-backed coplanar waveguide (CBCPW) structures and metal-insulator-metal (MIM) capacitors. A double-stub low Q input matching network is design to achieve wideband input matching. Since one of double-stub is open stub, the S11 can easily be tuned by trimming after fabrication. Load-pull simulation generates the optimal load impedance. A wideband harmonic rejection ESD is introduced to simultaneously reject the harmonics and achieve ESD protection. Simulation result shows that the maximum gain is 35.4 dB with 3 dB bandwidth 55-69 GHz. The S11 is 1-10 dB in the 50-80 GHz. The output P1dB is 6.7 dBm and the saturated output power Psat is 8.9 dBm. The peak PAE is 12.8%. The chip size is 1050×280 μm2. It consumes 60mW from a 1.8V supply. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISOCC.2011.6138632 | ISOCC |
Keywords | DocType | ISBN |
bicmos integrated circuits,ge-si alloys,mim devices,capacitors,coplanar waveguides,design,electrostatic discharge,power amplifiers,bicmos technology,cbcpw structures,esd protection,mim capacitors,conductor-backed coplanar waveguide,design consideration,inter-stage matching,metal-insulator-metal capacitors,power amplifier,60 ghz,cpwg,esd,sige bicmos,harmonic rejection,coplanar waveguide,chip | Conference | 978-1-4577-0710-0 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Keping Wang | 1 | 8 | 4.42 |
| Kaixue Ma | 2 | 38 | 19.01 |
| Kiat Seng Yeo | 3 | 365 | 63.72 |