Name
Abstract | ||
|---|---|---|
We consider a new generation of COTS software routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR networking performance and behavior. To this purpose, we separately characterized the roles of both HW and SW layers through a large set of internal and external experimental measurements, obtained with a heterogeneous set of HW platforms and SR setups. Starting from this detailed measure analysis, we propose a simple model, able to represent the SR performance with a high accuracy level in terms of packet throughput and related power consumption. The proposed model can be effectively applied inside "green optimization" mechanisms in order to minimize power consumption, while maintaining a certain SR performance target. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICC.2009.5199050 | Dresden |
Keywords | Field | DocType |
computer network performance evaluation,microprocessor chips,power aware computing,software packages,COTS software routers,PC-based software router,green optimization mechanisms,multicore-CPU HW platforms,packet throughput,performance evaluation,performance modeling,power consumption,power saving mechanisms | Power saving,Computer science,Network packet,Computer network,Exploit,Real-time computing,Software,Performance measurement,Throughput,Software router,Power consumption,Embedded system | Conference |
ISSN | ISBN | Citations |
1938-1883 E-ISBN : 978-1-4244-3435-0 | 978-1-4244-3435-0 | 28 |
PageRank | References | Authors |
2.46 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Raffaele Bolla | 1 | 736 | 69.90 |
| Roberto Bruschi | 2 | 151 | 19.65 |
| Andrea Ranieri | 3 | 69 | 8.28 |