Name
Title | ||
|---|---|---|
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy |
Abstract | ||
|---|---|---|
Decreasing operating margins due to random variations is a key issue for voltage scaling in SRAM technology. It is particularly severe for half-select disturb because both write and read occur at the same row. While a wordline (WL) voltage assist technique [1] does not improve half-select disturbs, a negative bitline (BL) scheme [2] or asymmetric pass gate (PG) transistor with higher VTH during read [3] can be effective for mitigating half-select disturbs. While these techniques can increase operating margins, they cannot specifically target cells to correct for random variations. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISSCC.2012.6176989 | Solid-State Circuits Conference Digest of Technical Papers |
Keywords | Field | DocType |
SRAM chips,transistors,6T SRAM,asymmetric pass gate transistor,carrier-injection scheme,negative bitline scheme,voltage scaling,wordline voltage assist technique | Logic gate,Computer science,Voltage,Static random-access memory,Electronic engineering,Pass gate,Transistor,Electrical engineering,Scaling,Maintenance engineering | Conference |
ISSN | ISBN | Citations |
0193-6530 | 978-1-4673-0376-7 | 4 |
PageRank | References | Authors |
0.46 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kousuke Miyaji | 1 | 59 | 9.73 |
| Toshi-kazu Suzuki | 2 | 73 | 11.00 |
| Shinji Miyano | 3 | 85 | 12.63 |
| Ken Takeuchi | 4 | 88 | 43.27 |