Paper Info
Title
An Energy Efficient Multi-Core Modem Architecture for LTE Mobile Terminals
Abstract
Since data rate in wireless communication systems has exponentially increased during the last decade, serious efforts are considered to fulfill their target requirements. Therefore, providing a satisfactory hardware to support high data rates while minimizing power consumption is a key design challenge for Long Term Evolution (LTE) mobile terminals. In this paper we introduce an optimized parallel software architecture for LTE mobile terminals using an energy aware scheduling and load balancing. We show that the proposed software architecture on single, dual, triple and quad-core hardware platforms leads to up to 39% energy savings. In addition, different hardware design options are investigated in order to minimize the average power consumption. The homogeneous multi-core with four cores processing the optimized LTE software saves about one quarter of the energy compared to a single-core running at higher clock frequency achieving the same data rate. Considering statistics for the mobile user behavior, the homogeneous multi-core with four cores proves to provide the minimum average power consumption compared to the other hardware architectures considered in this work.
Year
DOI
Venue
2012
10.1109/NTMS.2012.6208675
New Technologies, Mobility and Security
Keywords
Field
DocType
Long Term Evolution,energy conservation,multiprocessing systems,optimisation,parallel architectures,resource allocation,scheduling,software architecture,telecommunication terminals,LTE,clock frequency,data rate,energy aware scheduling,energy efficiency,energy saving,hardware architecture,hardware design,load balancing,long term evolution,mobile terminal,multicore modem architecture,optimization,parallel software architecture,statistics,wireless communication system
Energy conservation,Desktop and mobile Architecture for System Hardware,Computer science,Efficient energy use,Load balancing (computing),Scheduling (computing),Computer network,Software architecture,Multi-core processor,Clock rate,Embedded system
Conference
ISSN
ISBN
Citations 
2157-4952 E-ISBN : 978-1-4673-0227-2
978-1-4673-0227-2
2
PageRank 
References 
Authors
0.38
8
3
Name
Order
Citations
PageRank
Anas Showk1143.22
Shadi Traboulsi2284.50
Attila Bilgic36911.72