Paper Info
Title
Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches
Abstract
The paper elaborates on a kind of positive feedback latch that is not used as a memory element but rather for purposes of complementary signal edge alignment and digital output signal speed-up. The theoretical background behind positive exponential rise latches is presented in detail. The proposed latch is fully differential, fully complementary and perfectly symmetrical. It is structurally composed through comparisons with the set-reset (SR) latch and is implemented in CMOS technology. Simulation results show that the proposed circuit improves the state switching ability thus relaxing the design constraints connected to the latch interface. The latch, hence allows larger optimization space which leads to a better design.
Year
DOI
Venue
2012
10.1109/DDECS.2012.6219088
Design and Diagnostics of Electronic Circuits & Systems
Keywords
Field
DocType
CMOS integrated circuits,flip-flops,CMOS technology,complementary edge alignment,complementary signal edge alignment,digital output signal speed-up CMOS positive feedback latches,latch interface,memory element,optimization space,positive exponential rise latches,set-reset latch,state switching ability
State switching,Exponential function,Computer science,Electronic engineering,Real-time computing,Positive feedback,CMOS,Signal edge,Speedup
Conference
ISSN
ISBN
Citations 
2334-3133
978-1-4673-1186-1
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Vladimir Milovanovic100.34
H. Zimmermann25715.95