Name
Title | ||
|---|---|---|
A systematic M safe-error detection in hardware implementations of cryptographic algorithms |
Abstract | ||
|---|---|---|
This paper presents a procedure that checks whether a hardware implementation of a cryptographic algorithm is vulnerable to M safe-error attacks. It takes a registertransfer level (RTL) description of a design as an input and exposes the exact timing and a memory element that is a possible target of the attack. As a proof of concept, the presented procedure is applied to a hardware implementation of the Montgomery Powering Ladder, an exponentiation algorithm commonly used in public-key cryptography. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/HST.2012.6224327 | Hardware-Oriented Security and Trust |
Keywords | Field | DocType |
digital arithmetic,public key cryptography,M safe-error attacks,RTL,cryptographic algorithms,exact timing,exponentiation algorithm,hardware implementations,memory element,montgomery powering ladder,public-key cryptography,register transfer level description,systematic M safe-error detection,Fault attacks,Fault detection,M safe-errors,RTL description | Hardware implementations,Cryptography,Fault detection and isolation,Computer science,Algorithm,Real-time computing,Error detection and correction,Proof of concept,Exponentiation,Public-key cryptography | Conference |
ISBN | Citations | PageRank |
978-1-4673-2341-3 | 1 | 0.35 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dusko Karaklajic | 1 | 1 | 0.35 |
| Junfeng Fan | 2 | 334 | 29.09 |
| Ingrid Verbauwhede | 3 | 19 | 4.83 |