Name
Abstract | ||
|---|---|---|
Post-silicon validation, i.e., physical characterization of a small number of fabricated circuit instances before start of high-volume manufacturing, has become an essential step in integrated circuit production. Post-silicon validation is required to identify intricate logic or electrical bugs which could not be found during pre-silicon verification. In addition, physical characterization is useful to determine the performance distribution of the manufactured circuit instances and to derive performance yield. Test vectors used for this step are subject to different requirements compared to vectors for simulation-based verification or for manufacturing test. In particular, they must sensitize a very comprehensive set of paths in the circuit, assuming massive variations and possible modeling deficiencies. An inadequate test vector set may result in overly optimistic yield estimates and wrong manufacturing decisions. On the other hand, the size of the test vector set is less important than in verification or manufacturing test. In this paper, we systematically investigate the relationship between the quality of the employed test vectors and the accuracy of yield-performance predictions. We use a highly efficient SAT-based algorithm to generate comprehensive test vector sets based on simple model assumptions and validate these test sets using simulated circuit instances which incorporate effects of process variations. The obtained vector sets can also serve as a basis for adaptive manufacturing test. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ETS.2012.6233027 | European Test Symposium |
Keywords | Field | DocType |
elemental semiconductors,integrated circuit design,integrated circuit manufacture,integrated circuit testing,silicon,vectors,SAT-based algorithm,Si,circuit fabrication,circuit manufacturing testing,electrical bug,integrated circuit production,logic bug,optimistic yield estimation,post-silicon characterization,pre-silicon verification,simulation-based verification,test vector set quality,yield-performance prediction,ATPG,Post-silicon validation,adaptive test,delay faults,performance yield | Test method,Test vector,Automatic test pattern generation,Post-silicon validation,Computer science,Software bug,Real-time computing,Electronic engineering,Integrated circuit design,Computerized adaptive testing,Integrated circuit | Conference |
ISSN | ISBN | Citations |
1530-1877 | 978-1-4673-0695-9 | 6 |
PageRank | References | Authors |
0.41 | 16 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Sauer | 1 | 195 | 20.02 |
| Alexander Czutro | 2 | 56 | 4.53 |
| Bernd Becker | 3 | 855 | 73.74 |
| Ilia Polian | 4 | 889 | 78.66 |