Name
Abstract | ||
|---|---|---|
This session of exclusively invited papers covers a selection of wafer-level technology developments key to extending nanoscale CMOS. Specific topics are progress and outlook of lithography, copper interconnects, SOI-CMOS device architectures, and high-mobility channel CMOS technologies. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CICC.2009.5280902 | San Jose, CA, USA |
Keywords | Field | DocType |
cmos integrated circuits,logic gates,copper,data mining,lithography,cmos technology | Logic gate,Nanoscale cmos,Computer science,Communication channel,Electronic engineering,CMOS,Lithography,Cmos scaling,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4244-4073-3 | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takamaro Kikkawa | 1 | 69 | 14.32 |
| Lai, Jordan | 2 | 0 | 0.34 |