Name
Title | ||
|---|---|---|
Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing |
Abstract | ||
|---|---|---|
In this paper, we address the problem of an efficient mapping of intellectual property (IP) cores onto a multiprocessor system-on-chip (MPSoC). The MPSoC is statically scalable in terms of number of IP cores and an 1-ary n-mesh network-on-chip (NoC). The approach places more affine IP cores closer to each other and affinity is based on an amount of exchanged communication and administration data. Assuming ideal network conditions, accounting for execution latency, separate affinity value matrices for communication and administration are extracted from the application mappings. Aiming at better system performance, the goal is to find a reasonable tradeoff between communication and administration affinity. Hence, both matrices are merged into a single affinity value matrix based on linear weighting. A genetic algorithm (GA) and a mixed-integer linear programming (MILP) solution use the weighted affinity value matrix to efficiently map IP cores onto a NoC. A scalability analysis shows that the GA generates results faster and with a satisfactory quality relative to the found MILP solutions. Realistic benchmark results demonstrate that a tradeoff between administration and communication affinity significantly reduces administration latency improving application performance. As network size and system adaptability increase, the growing influence of administration becomes more evident. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/CEC.2012.6256115 | IEEE Congress on Evolutionary Computation |
Keywords | Field | DocType |
genetic algorithms,industrial property,integer programming,linear programming,multiprocessing systems,network-on-chip,1-ary n-mesh network-on-chip,GA,IP cores,IP mapping,MILP solution,MPSoC,NoC,accounting,administration affinity,administration data,administration latency,administration-aware IP core mapping,communication-aware IP core mapping,evolutionary computing,execution latency,genetic algorithm,ideal network conditions,intellectual property,linear weighting,mixed-integer linear programming,scalability analysis,scalable multiprocessor system-on-chips,separate affinity value matrices,single affinity value matrix,system adaptability,weighted affinity value matrix,IP core mapping,evolutionary computing,evolutionary design,network-on-chip design | Computer science,Parallel computing,Evolutionary computation,Network on a chip,Multiprocessing,Integer programming,Linear programming,MPSoC,Genetic algorithm,Scalability | Conference |
ISBN | Citations | PageRank |
978-1-4673-1508-1 | 1 | 0.35 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Falko Guderian | 1 | 3 | 1.15 |
| Rainer Schaffer | 2 | 2 | 0.72 |
| Gerhard Fettweis | 3 | 1 | 0.35 |