Paper Info
Title
Location Cache Design and Performance Analysis for Chip Multiprocessors
Abstract
Recent research at Intel suggests that chips with hundreds of processor cores are possible in the not-so-distant future. As the number of cores grows, so does the size of the cache systems required to allow them to operate efficiently. Caches have grown to consume a significant percentage of the power utilized by a processor. In this research, we extend the concept of location cache to support chip multiprocessors (CMPs) systems in combination with low-power L2 caches based upon the gated-ground technique. The combination of these two techniques allows for reductions in both dynamic and leakage power consumption. In this paper, we will present an analysis of the power savings provided by utilizing location caches in a CMP system. The performance of the cache system is evaluated by extending the capability of CACTI and Simics using the SPLASH-2 and ALPBench benchmark suites. These simulation results demonstrate that the utilization of location caches in CMP systems is capable of saving a significant amount of power over equivalent CMP systems that lack location caches.
Year
DOI
Venue
2011
10.1109/TVLSI.2009.2028429
VLSI) Systems, IEEE Transactions
Keywords
Field
DocType
cache storage,microprocessor chips,ALPBench benchmark suite,CACTI,Intel,L2 caches,SPLASH-2 benchmark suite,Simics,chip multiprocessors system,gated-ground technique,location cache design,performance analysis,Cache architecture,dynamic and leakage power dissipation,gated ground technique,location cache,low-power design,power analysis
Power analysis,Cache,Computer science,CPU cache,Cache-only memory architecture,Electronic engineering,Real-time computing,Simics,Multi-core processor,Parallel computing,Multiprocessing,Bus sniffing,Embedded system
Journal
Volume
Issue
ISSN
19
1
1063-8210
Citations 
PageRank 
References 
3
0.38
15
Authors
4
Name
Order
Citations
PageRank
Jason Nemeth130.38
Rui Min25110.33
Wen-Ben Jone341946.30
Yiming Hu463944.91