Name
Abstract | ||
|---|---|---|
Delay variation due to dopant fluctuation is expected to become more prominent in future technology generations. To regain performance lost due to within-die variations, many architectural techniques propose modified timing schemes such as time borrowing or variable latency execution. As an alternative that specifically targets random variation, we propose introducing redundancy along the processor datapath in the form of one or more extra bitslices. This approach allows us to leave dummy slices in the datapath unused to avoid excessively slow critical paths created by delay variations. We examine the benefits of applying this technique to potential critical paths such as the ALU and register file, and demonstrate that our technique can significantly reduce the delay penalty due to variation. By adding a single bitslice, for instance, we can reduce this delay penalty by 10%. Finally, we discuss heuristics for configuring our redundant design after fabrication. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/DSN.2012.6263952 | Dependable Systems and Networks |
Keywords | Field | DocType |
digital arithmetic,integrated circuit design,microprocessor chips,ALU,delay variation,dopant fluctuation,random variation mitigation,redundant intermediate bitslices,register file,spare RIB,time borrowing,timing schemes,variable latency execution,bitsliced design,doping,performance,process variation,reliability | Datapath,Random variable,Computer science,Latency (engineering),Register file,Real-time computing,Integrated circuit design,Heuristics,Redundancy (engineering),Process variation,Distributed computing | Conference |
ISSN | ISBN | Citations |
1530-0889 E-ISBN : 978-1-4673-1623-1 | 978-1-4673-1623-1 | 3 |
PageRank | References | Authors |
0.42 | 19 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David J. Palframan | 1 | 68 | 3.90 |
| Nam Sung Kim | 2 | 3268 | 225.99 |
| Mikko H. Lipasti | 3 | 313 | 23.29 |