Name
Abstract | ||
|---|---|---|
For robust design of SRAM memories, it is not sufficient to guarantee good statistical margins on the SRAM cell parameters. The sense amplifier needs sufficient input signal before it can reliably sense the data, while the SRAM cell requires sufficient time to develop that input signal. This paper presents a new statistical method that allows optimization of the access time of an SRAM memory, while guaranteeing a yield target set by the designer. Using this method, the access time of a high performance advanced CMOS SRAM has been improved 6%, while simultaneously reducing the sense amplifier size. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ESSCIRC.2009.5325954 | european solid-state circuits conference |
Keywords | DocType | ISSN |
CMOS memory circuits,SRAM chips,amplifiers,circuit optimisation,integrated circuit design,statistical analysis,SRAM active column optimization,SRAM cell parameters,SRAM memories robust design,high performance advanced CMOS SRAM,sense amplifier size reduction,yield centric statistical design method | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4244-4354-3 | 0 | 0.34 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toby Doorn | 1 | 26 | 3.07 |
| Croon, J.A. | 2 | 0 | 0.34 |
| E. J. W. ter Maten | 3 | 0 | 0.34 |
| Di Bucchianico, A. | 4 | 0 | 0.34 |