Name
Abstract | ||
|---|---|---|
In this paper, we present the basic concepts of invasive computing and subsequently analyze the performance overheads of invasive computing applications on several multi- and many-core architectures. The nature of these is to claim and free resources dynamically at run-time to increase resource efficiency of future MPSoC architectures while not sacrificing speedup in comparison to traditional, statically mapped applications. This holds true especially for programs with highly dynamic parallelism profiles. Based on a formal notation of speedup and resource efficiency for invasive parallel programs, we present a real SPARC LEON-based MPSoC system implementation to evaluate achievable resource efficiencies for realistic workload scenarios showing that the real-measured overhead of invasion can be kept very low and resource efficiencies of up to 100% will become possible without a considerable drop in speedup compared to non-invasive programs using statically allocated resources. Also, we present invasion overheads for tightly-coupled processor arrays (TCPAs) that avoid the creation of threads and use hardware-based signaling concepts to invade processing elements. Finally, we present results how expensive invasive computing overheads may be by proposing two implementations on existing MPSoC platforms, namely the Tilera TilePro64 architecture and on Intel's SCC for comparison. |
Year | Venue | Keywords |
|---|---|---|
2012 | Specification and Design Languages | computer architecture,multiprocessing systems,parallel programming,resource allocation,system-on-chip,Intel SCC,SPARC LEON-based MPSoC system,TCPA,Tilera TilePro64 architecture,dynamic parallelism profiles,future MPSoC architectures,hardware-based signaling concepts,invasion overheads,invasive computing,invasive parallel programs,many-core architectures,multicore architectures,performance overhead analysis,resource efficiency,thread creation avoidance,tightly-coupled processor arrays,workload scenarios |
Field | DocType | ISSN |
Computer architecture,System on a chip,TILEPro64,Resource efficiency,Computer science,Thread (computing),Real-time computing,Resource allocation,MPSoC,Speedup,Embedded system,Overhead (business) | Conference | 1636-9874 |
ISBN | Citations | PageRank |
978-1-4673-1240-0 | 4 | 0.43 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jürgen Teich | 1 | 24 | 3.69 |
| Andreas Weichslgartner | 2 | 4 | 1.10 |
| Benjamin Oechslein | 3 | 4 | 0.43 |
| Wolfgang Schröder-Preikschat | 4 | 896 | 90.63 |