Name
Abstract | ||
|---|---|---|
Due to increasing CMOS process variability, optimization for yield has become one of the crucial tasks in Integrated Circuit (IC) design especially in analog IC design. This variability is getting worse with the continuous scaling of device dimensions and therefore degrades the IC fabrication outcome. This paper presents the yield optimization for low power second generation dual output current controlled current conveyor (DOCCCII). Current conveyors (CC) are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net list of given DOCCCII circuit has been simulated in Eldo using 65nm CMOS mixed signal Low-K IMD TSMC process development kit (PDK) with ±0.6V, low-Vt devices with statistical models. All verification, sizing and optimization analysis have been performed using the commercially available WiCkeD toolset from MunEDA at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/SBCCI.2012.6344426 | Integrated Circuits and Systems Design |
Keywords | Field | DocType |
CMOS analogue integrated circuits,Monte Carlo methods,current conveyors,integrated circuit design,CMOS process variability,Eldo,IC fabrication,IMD TSMC process development kit,Monte Carlo analysis,MunEDA,WiCkeD toolset,analog IC design,bias current,continuous scaling,device dimension,electronic tunability,integrated circuit design,intrinsic resistance terminal,low power current controlled current conveyor,second generation dual output current controlled current conveyor,size 65 nm,statistical model,yield optimization,DOCCCII,Monte Carlo,Worst case distance,Yield,deterministic nominal optimization,feasibility | Computer science,Semiconductor device fabrication,Chip,Electronic engineering,CMOS,Integrated circuit design,Mixed-signal integrated circuit,Current conveyor,Electrical engineering,Integrated circuit,Biasing | Conference |
ISBN | Citations | PageRank |
978-1-4673-2606-3 | 0 | 0.34 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abbas, Z. | 1 | 0 | 0.34 |
| Yakupov, M. | 2 | 0 | 0.34 |
| Olivieri, N. | 3 | 0 | 0.34 |
| Ripp, A. | 4 | 0 | 0.34 |