Name
Abstract | ||
|---|---|---|
This paper presents a wide-range I/O buffer able to transmit and receive signals of 0.9/1.2/1.8/3.3/5.0 V by using a typical 0.18 μm CMOS process. The Dynamic gate bias circuit in the proposed I/O buffer is composed of two voltage converters, an EOS (Electrical Overstress) protector, and standard logic cells. A High voltage detector detects voltage level of VDDIO and then generates several bias voltages to the Dynamic gate bias circuit. By using the Dynamic gate bias generator to generate appropriate gate drives for the triple-stacked MOS transistors in the Output stage, the gate-oxide overstress and hot-carrier degradation are avoided. A Floating N-well circuit in the proposed I/O buffer is used to remove undesirable leakage current paths. The proposed I/O buffer can operate at 10/40/50/40/10 MHz when VDDIO are biased at 5.0/3.3/1.8/1.2/0.9 V, respectively. The maximum speed is 50 MHz given a 19 pF load. The maximum static power consumption is merely 3.9 μW justified by the measurements on silicon. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSI.2009.2036054 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | Field | DocType |
cmos integrated circuits,mosfet,buffer circuits,logic circuits,cmos process,bidirectional i/o buffer,dynamic gate bias circuit,dynamic gate bias generator,logic cells,triple-stacked mos transistors,dynamic gate bias,i/o buffer,floating n-well,mixed-voltage tolerant,wide-range | Logic gate,Cmos process,Input/output,NAND gate,CMOS,Electronic engineering,MOSFET,Materials science,Gate equivalent,Electrical engineering | Journal |
Volume | Issue | ISSN |
57 | 7 | 1549-8328 |
Citations | PageRank | References |
1 | 0.43 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chua-chin Wang | 1 | 474 | 107.39 |
| Chia-Hao Hsu | 2 | 44 | 11.63 |
| Yi-Cheng Liu | 3 | 41 | 13.29 |