Paper Info
Title
Performance evaluation of NEC SX-9 using real science and engineering applications
Abstract
This paper describes a new-generation vector parallel supercomputer, NEC SX-9 system. The SX-9 processor has an outstanding core to achieve over 100Gflop/s, and a software-controllable on-chip cache to keep the high ratio of the memory bandwidth to the floating-point operation rate. Moreover, its large SMP nodes of 16 vector processors with 1.6Tflop/s performance and 1TB memory are connected with dedicated network switches, which can achieve inter-node communication at 128GB/s per direction. The sustained performance of the SX-9 processor is evaluated using six practical applications in comparison with conventional vector processors and the latest scalar processor such as Nehalem-EP. Based on the results, this paper discusses the performance tuning strategies for new-generation vector systems. An SX-9 system of 16 nodes is also evaluated by using the HPC challenge benchmark suite and a CFD code. Those evaluation results clarify the highest sustained performance and scalability of the SX-9 system.
Year
DOI
Venue
2009
10.1145/1654059.1654088
Portland, OR
Keywords
Field
DocType
cache storage,parallel machines,performance evaluation,CFD code,HPC challenge benchmark suite,NEC SX-9 system,Nehalem-EP,SMP node,SX-9 processor,floating-point operation rate,internode communication,memory bandwidth,network switches,new-generation vector parallel supercomputer,new-generation vector system,performance evaluation,performance tuning strategy,scalar processor,software-controllable on-chip cache,vector processor
Memory bandwidth,Scalar processor,Supercomputer,Cache,Computer science,Parallel computing,Vector processor,Computer hardware,HPC Challenge Benchmark,Performance tuning,Distributed computing,Scalability
Conference
Citations 
PageRank 
References 
18
1.41
5
Authors
4
Name
Order
Citations
PageRank
Takashi Soga1364.26
Musa, A.2432.27
Shimomura, Y.3181.41
Egawa, R.4181.41