Name
Title | ||
|---|---|---|
Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement |
Abstract | ||
|---|---|---|
In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.
|
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ASPDAC.2010.5419855 | Design Automation Conference |
Keywords | Field | DocType |
CMOS integrated circuits,field programmable gate arrays,CMOS multicontext FPGA,delay measurement,flexible processor,reconfigurable multicontext FPGA,shift-register temporal communication module,size 90 nm,temporal circuit partitioning,temporal partitioning | Computer science,Latency (engineering),Field-programmable gate array,CMOS,Real-time computing,Electronic engineering,Critical path method | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-5767-0 | 1 |
PageRank | References | Authors |
0.36 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naoto Miyamoto | 1 | 4 | 3.27 |
| Tadahiro Ohmi | 2 | 114 | 36.98 |