Title
A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Abstract
Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6 T SRAM cells. To overcome this limitation, 7 T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6 T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6 T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7 T TFET SRAM cell. We achieve a leakage reduction improvement of 700 X and 1600 X over traditional CMOS SRAM designs at VDD of 0.3 V and 0.5 V respectively which makes it suitable for use at ultra-low power applications.
Year
DOI
Venue
2010
10.1109/ASPDAC.2010.5419897
asia and south pacific design automation conference
Keywords
Field
DocType
CMOS memory circuits,SRAM chips,elemental semiconductors,field effect transistors,low-power electronics,silicon,tunnel transistors,CMOS SRAM designs,MOSFET,Si,inter-band tunnel field effect transistors,steep sub-threshold transistors,sub-threshold leakage reduction,tunnel FET,unidirectional current,voltage 0.3 V,voltage 0.5 V
Leakage (electronics),Stability margin,Field-effect transistor,Computer science,Voltage,CMOS,Static random-access memory,Electronic engineering,Transistor,Electrical engineering,Low-power electronics
Conference
ISSN
ISBN
Citations 
2153-6961
978-1-4244-5767-0
26
PageRank 
References 
Authors
3.96
3
6
Name
Order
Citations
PageRank
Jawar Singh17515.39
Ramakrishnan, K.2484.83
Mookerjea, S.3263.96
Suman Datta441551.93
Narayanan Vijaykrishnan56955524.60
D. Pradhan6263.96