Name
Abstract | ||
|---|---|---|
In this paper we propose a PLL based frequency synthesizer architecture having low spur. Using an array of switched capacitors and a delay locked loop (DLL), a periodic charge distribution technique to suppress reference spur in the PLL has been adopted. The DLL provides the equispaced M instances at which the capacitor array distributes the charge. For the validation of the concept, an integer-N frequency synthesizer with four times repetition of ripples for 916 MHz output frequency and 2 MHz input reference frequency, has been designed in 180 nm CMOS technology. Cadence Spectre simulation shows output spur improvement, with respect to a conventional architecture, of about 59, 75 and 65 dB respectively at 2, 4, 6 MHz offset frequencies while the spur at 8 MHz offset remains unchanged. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISOCC.2012.6407049 | ISOCC |
Keywords | DocType | ISSN |
cmos integrated circuits,delay lock loops,frequency synthesizers,phase locked loops,switched capacitor networks,cmos technology,cadence spectre simulation,pll,pll based frequency synthesizer architecture,delay locked loop,frequency 2 mhz,frequency 916 mhz,integer-n frequency synthesizer,periodic charge distribution technique,reference spur suppression,size 180 nm,switched capacitor array,spur suppression,charge distribution,frequency synthesizer,phase locked loop (pll),switched capacitor | Conference | 2163-9612 |
ISBN | Citations | PageRank |
978-1-4673-2988-0 | 9 | 1.33 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Debashis Mandal | 1 | 15 | 3.24 |
| Pradip Mandal | 2 | 10 | 1.70 |
| T. K. Bhattacharyya | 3 | 28 | 9.09 |