Name
Abstract | ||
|---|---|---|
Traditional ADC architectures often fail to provide the required balance between low-power and high sampling rate, leaving room for further topology exploration. We propose a modified binary search ADC topology, which relies on a pipeline for the comparator stages and tracks the input in a time-interleaved fashion. Extensive statistical simulations for the 4-bit proposed ADC show that, sampling at 1.5GSps, the ADC consumes 4.2mW, providing 3.67 effective bits and a figure of merit of 219fJ/conversion step, without requiring calibration. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ICECS.2012.6463700 | Electronics, Circuits and Systems |
Keywords | Field | DocType |
analogue-digital conversion,comparators (circuits),network topology,statistical analysis,ADC architectures,binary search ADC topology,comparator-based binary search ADC,statistical simulations,time-interleaved fashion | 4-bit,Comparator,Computer science,Sampling (signal processing),Effective number of bits,Network topology,Flash ADC,Electronic engineering,Binary search algorithm,Successive approximation ADC | Conference |
ISBN | Citations | PageRank |
978-1-4673-1259-2 | 1 | 0.43 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taimur Gibran Rabuske | 1 | 28 | 6.53 |
| Fabio Gibran Rabuske | 2 | 1 | 0.43 |
| Jorge R. Fernandes | 3 | 154 | 34.16 |
| Cesar Ramos Rodrigues | 4 | 30 | 7.05 |