Name
Abstract | ||
|---|---|---|
Interconnect has become preponderant in many aspects of circuit design, namely delay, power and area. This effect is particularly true for FPGAs, where interconnect is often the most limiting factor. Quaternary logic offers a means to reduce interconnect since each circuit wire can, in principle, carry the same information as two binary wires. We have proposed in [1] a design implementing a quaternary low-power high-speed look-up table. The main features of this circuit are being based on a voltage-mode structure and using only standard CMOS technology. In this paper we present the design of a prototype implementation and experimental results. These results are discussed and conclusions are drawn that provide further guidelines for improvement. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ICECS.2012.6463744 | Electronics, Circuits and Systems |
Keywords | Field | DocType |
CMOS integrated circuits,field programmable gate arrays,integrated circuit interconnections,LC resonators,bandpass sigma-delta modulator,feedback signals,loop delays,one time-interleaved resonator,time-interleaved resonators,undersampled BP ΣΔ modulator | Computer science,Circuit extraction,Circuit design,Electronic engineering,CMOS,Application-specific integrated circuit,Physical design,Mixed-signal integrated circuit,Integrated circuit,Equivalent circuit | Conference |
ISBN | Citations | PageRank |
978-1-4673-1259-2 | 1 | 0.41 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Diogo Brito | 1 | 1 | 0.75 |
| Jorge R. Fernandes | 2 | 154 | 34.16 |
| Paulo Flores | 3 | 270 | 25.28 |
| Jose Monteiro | 4 | 660 | 128.33 |