Paper Info
Title
A 256-Mcell Phase-Change Memory Chip Operating at Bit/Cell
Abstract
A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on-chip circuitry supports fast MLC operation at 4 bit/cell. A programmable digital controller is used to optimize closed-loop gain and timing of the iterative MLC programming scheme and two power-efficient 8-bit DACs support current-controlled as well as voltage-controlled write pulses. The read-out consists of a low-power auto-range frontend followed by a 6-bit cyclic ADC that converts the nonlinear PCM resistance in a range between 10 kΩ and 10 MΩ . A verilog-A model derived from a full 3-D simulation of the PCM cell was developed to simulate the complete chip. The chip was used to demonstrate operation at 2 bit/cell and programming below 10 μs with Ge 2Sb 2Te 5 (GST) based PCM cells at a raw bit error rate of ~ 2 × 10- 4. Two main roadblocks for MLC PCM are drift and endurance. The accuracy of the analog frontend in combination with the programmable controller enables drift mitigation at the system level and the exploration of new materials for MLC operation at 3+ bit/cell.
Year
DOI
Venue
2013
10.1109/TCSI.2012.2220459
Circuits and Systems I: Regular Papers, IEEE Transactions
Keywords
DocType
Volume
CMOS memory circuits,phase change memories,programmable controllers,ADC,CMOS technology,DAC,bit error rate,closed-loop gain,current-controlled write pulses,iterative MLC programming scheme,on-chip circuitry,phase-change memory chip,programmable digital controller,resistance 10 Mohm,resistance 10 kohm,verilog-A model,voltage-controlled write pulses,wavelength 90 nm,word length 6 bit,word length 8 bit,Multi-level cell,PCM,nonvolatile memory,phase-change memory
Journal
60
Issue
ISSN
Citations 
6
1549-8328
3
PageRank 
References 
Authors
0.44
0
4
Name
Order
Citations
PageRank
Close, G.F.130.44
Frey, U.230.44
Morrish, J.330.44
Jordan, R.491.92