Paper Info
Title
Software-defined DVB-T2 receiver using coarse-grained reconfigurable array processors
Abstract
This paper describes the feasibility of software implementation of DVB-T2 receiver with DTG-106 [1] mode using the coarse-grained reconfigurable array (CGRA) based processor. This paper focuses mainly on DVB-T2 system design and implementation of major software functions of DVB-T2 demodulator: FFT, frequency interpolation, multi-level de-interleaving, and soft-demapper. By implementing the full chain DVB-T2 software and measuring the cycle performance, we demonstrate the software implantation of DVB-T2 on dual core CGRA processor running at 400MHz.
Year
DOI
Venue
2013
10.1109/ICCE.2013.6487026
ICCE
Keywords
Field
DocType
fast fourier transforms,interpolation,microprocessor chips,software engineering,telecommunication computing,television broadcasting,television receivers,dtg-106 mode,dvb-t2 demodulator,fft function,coarse-grained reconfigurable array,digital terrestrial television broadcasting system,dual core cgra processor,fast fourier transform,interpolation function,multilevel deinterleaving function,soft-demapper function,software-defined dvb-t2 receiver
Broadcasting,Demodulation,DVB-T2,Computer science,Interpolation,Systems design,Electronic engineering,Digital television,Fast Fourier transform,Software
Conference
ISSN
ISBN
Citations 
2158-3994
978-1-4673-1361-2
5
PageRank 
References 
Authors
0.52
2
5
Name
Order
Citations
PageRank
Navneet Basutkar1172.00
Ho Yang2316.03
Peng Xue3153.06
Kitaek Bae4537.08
Young-Hwan Park510910.35