Name
Title | ||
|---|---|---|
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs |
Abstract | ||
|---|---|---|
This paper proposes a floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISCAS.2010.5537402 | Circuits and Systems |
Keywords | Field | DocType |
asynchronous circuits,circuit layout,delays,field programmable gate arrays,FPGA,asynchronous circuits,control circuit,delay,floorplan method,timing constraints | Asynchronous communication,Computer architecture,Computer science,Field-programmable gate array,Electronic engineering,Electronic circuit,Floorplan | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-5309-2 | 6 |
PageRank | References | Authors |
0.58 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroshi Saito | 1 | 22 | 4.82 |
| Naohiro Hamada | 2 | 16 | 2.76 |
| Tomohiro Yoneda | 3 | 353 | 41.62 |
| Takashi Nanya | 4 | 200 | 35.46 |