Name
Abstract | ||
|---|---|---|
This paper presents an effective Cycle-Count Accurate Transaction Level Modeling (CCA-TLM) and simulation technique for a point-to-point bus. We propose a two-phase bus arbitration model and an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture validation and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs. The experiment results show that the proposed approach performs 23 times faster than the Cycle-Accurate (CA) bus model while maintaining 100% accurate timing information at every transaction boundary. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLDI-DAT.2013.6533807 | VLSI Design, Automation, and Test |
Keywords | Field | DocType |
integrated circuit design,integrated circuit modelling,multiprocessing systems,system-on-chip,transmission lines,ca bus model,cmsat model,fsm-based composite master-slave-pair and arbiter transaction model,bus architecture validation,complex multiprocessor system-on-chip design contention analysis,cycle count accurate tlm bus modeling approach,cycle-count accurate transaction level modeling,point-to-point bus simulation technique,two-phase bus arbitration model,system on chip | Arbiter,Computer science,Parallel computing,Transaction-level modeling,Cycle count,Real-time computing,Local bus,Back-side bus,MPSoC,System bus,Control bus | Conference |
ISSN | ISBN | Citations |
2474-2724 | 978-1-4673-4435-7 | 0 |
PageRank | References | Authors |
0.34 | 5 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mao-Lin Li | 1 | 9 | 2.24 |
| Chen-Kang Lo | 2 | 44 | 2.98 |
| Li-Chun Chen | 3 | 0 | 0.34 |
| Jen-Chieh Yeh | 4 | 223 | 21.72 |
| Tsay, Ren-Song | 5 | 368 | 72.19 |