Title
RF BIST and test strategy for the receive part of an RF transceiver in CMOS technology
Abstract
This paper focuses on the RF BIST architecture of the receive path of an RF transceiver processed in the NXP in house CMOS technology with 0.14μm gate length.
Year
DOI
Venue
2013
10.1109/ETS.2013.6569387
Test Symposium
Keywords
Field
DocType
CMOS integrated circuits,built-in self test,integrated circuit testing,radio transceivers,CMOS technology,NXP,RF BIST architecture,RF transceiver,receive part,receive path,size 0.14 mum
Phase-locked loop,Transceiver,Computer science,Attenuator (electronics),CMOS,Radio frequency,Electronic engineering,Electrical engineering,Test strategy,Built-in self-test,Gain measurement
Conference
ISSN
ISBN
Citations 
1530-1877
978-1-4673-6376-1
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Christophe Kelma1495.21
Sébastien Darfeuille271.99
Andreas Neuburger300.34
Andreas Lobnig400.34