Name
Abstract | ||
|---|---|---|
This paper presents a preliminary evaluation of the SEU Controller Macro, a VHDL component developed by Xilinx for the detection and recovery of single event upsets, as a building block of an FPGA fault-injector. We found that this SEU Controller Macro is extremely effective for injecting faults into the FPGA configuration memory, as single and double bit-flips, with precise location, virtually no intrusiveness, and coarse timing accuracy. We present some clues on how to extend its functionalities to build a fully-fledge FPGA fault injector. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/DSN.2013.6575336 | Dependable Systems and Networks |
Keywords | Field | DocType |
fault tolerant computing,field programmable gate arrays,hardware description languages,FPGA configuration memory,VHDL component,Xilinx SEU controller macro evaluation,double bit-flips,fault injection,field programmable gate arrays,single bit-flips,single event upset detection,single event upset recovery,FPGA,SEU,embedded systems,fault injection | Structured systems analysis and design method,Control theory,Computer science,Injector,Field-programmable gate array,Real-time computing,VHDL,Macro,Fault injection,Hardware description language,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-0889 | 978-1-4673-6471-3 | 1 |
PageRank | References | Authors |
0.40 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jose Luis Nunes | 1 | 1 | 0.40 |
| João Carlos Cunha | 2 | 61 | 13.55 |
| Raul Barbosa | 3 | 110 | 19.08 |
| Mário Zenha Rela | 4 | 124 | 16.53 |