Title
Memory-efficient FFT architecture using R-LFSR based CORDIC common operator
Abstract
In the Software Defined Radio (SDR) area, parameterization is becoming a very important topic in the design of multi-standard terminals. In this context, the Common Operator (CO) technique defines an open and optimized terminal based on a limited set of generic components called Common Operators. The method was already described in and a new relevant possible CO was presented: R-LFSR based CORDIC which is a result of synergy study between CORDIC and Reconfigurable LFSR. We present in this work an original FFT architecture based on the CORDIC in which R-LFSR is exploited. In this case, FFT functions which were performed by CORDIC can be performed by R-LFSR and vice-versa. The novel FFT architecture was successfully implemented on a FPGA Virtex-4 to compare with a FFT using conventional CORDIC. The complexity evaluation is presented.
Year
DOI
Venue
2010
10.1109/CIP.2010.5604220
CIP
Keywords
Field
DocType
digital arithmetic,fast fourier transforms,field programmable gate arrays,reconfigurable architectures,shift registers,software radio,fpga virtex-4,r-lfsr based cordic common operator,linear feedback shift register,memory-efficient fft architecture,multistandard terminal,reconfigurable lfsr,software defined radio,cordic,common operator,fft,lfsr,limit set,radio frequency
Shift register,Architecture,Software-defined radio,Computer science,Parallel computing,Field-programmable gate array,Radio frequency,Fast Fourier transform,CORDIC,Computational science,Operator (computer programming)
Conference
ISBN
Citations 
PageRank 
978-1-4244-6457-9
1
0.54
References 
Authors
6
5
Name
Order
Citations
PageRank
Hongzhi Wang164455.39
Yves Louët211223.96
Palicot, Jacques312213.87
Laurent Alaus4264.13
Dominique Noguet515616.97