Paper Info
Title
A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology
Abstract
A 4 Mb embedded phase change memory macro has been developed in a 90 nm 6-ML CMOS technology. The storage element has been integrated using 3 additional masks with respect to process baseline. The cell selector is implemented by a standard LV nMOS device, achieving a cell size of 0.29 μm2. A dual-voltage row decoder and a double-path column decoder are introduced, enabling a completely low voltage read operation. A 20b-parallelism write scheme is embedded in the digital controller in order to maximize throughput. In alternative, a power-saving low-parallelism write algorithm can be employed. The macro features a 1.2 V 12 ns read access time and a write throughput of 1 MB/s. Set and reset current distributions showing a good read window are presented and robust reliability results are demonstrated.
Year
DOI
Venue
2011
10.1109/JSSC.2010.2084491
Solid-State Circuits, IEEE Journal of
Keywords
Field
DocType
CMOS memory circuits,decoding,phase change memories,20b-parallelism write scheme,CMOS,LV nMOS device,bit rate 1 Mbit/s,cell selector,digital controller,double-path column decoder,dual-voltage row decoder,embedded phase change memory macro,masks,memory size 4 MByte,power-saving low-parallelism write algorithm,size 0.29 mum,size 90 nm,storage element,voltage 1.2 V,Charge pump,EEPROM,column decoder,embedded memory,embedded phase-change memory (ePCM),flash memory,non-volatile memory (NVM),phase-change memory (PCM),row decoder
EEPROM,Phase-change memory,Flash memory,NMOS logic,Access time,Computer science,Electronic engineering,CMOS,Non-volatile memory,Integrated circuit
Journal
Volume
Issue
ISSN
46
1
0018-9200
Citations 
PageRank 
References 
10
1.49
5
Authors
4
Name
Order
Citations
PageRank
De Sandre, G.1353.46
Luca Bettini26311.01
Pirola, A.3232.69
Marmonier, L.4101.49