Paper Info
Title
A 10-b 50-MS/s 820- W SAR ADC With On-Chip Digital Calibration
Abstract
This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm2 .
Year
DOI
Venue
2010
10.1109/TBCAS.2010.2081362
Solid-State Circuits Conference Digest of Technical Papers
Keywords
Field
DocType
CMOS digital integrated circuits,MIM devices,Nyquist criterion,analogue-digital conversion,calibration,capacitors,clocks,MIM capacitor,Nyquist condition,SAR ADC,SAR analog-to-digital converter,capacitor digital-to-analog converter,comparator offset cancellation,complementary metal-oxide semiconductor,frequency 25 MHz,internal clock control,linearity calibration,on-chip digital calibration,power 820 muW,size 65 nm,split-CDAC,voltage 1.0 V,Analog-to-digital converter (ADC),digital calibration,successive approximation register
Clock generator,Capacitor,Comparator,Computer science,Sampling (signal processing),CMOS,Electronic engineering,Successive approximation ADC,Electrical engineering,Operational amplifier,Clock rate
Conference
Volume
Issue
ISSN
4
6
1932-4545
ISBN
Citations 
PageRank 
978-1-4244-6033-5
26
2.67
References 
Authors
3
4
Name
Order
Citations
PageRank
Masato Yoshioka19112.46
Kiyoshi Ishikawa2262.67
Takeshi Takayama3262.67
Sanroku Tsukamoto410918.09