Name
Abstract | ||
|---|---|---|
In the paper we consider architecture of an analog dual delay locked loop (DLL). It uses an simply-implementable coarse delay line to push the loop close to lock state, and a fine programmable delay line to make small adjustments to the output phase. Both coarse- as well as fine-delay line are implemented as a cascades of variable-delay elements based on single-ended Schmitt triggers. For the correction of a duty cycle of the delayed output signal, particularly in the coarse delay segment, a very effective duty cycle correction (DCC) has been applied. The complete architecture of the DLL utilizing aforementioned building blocks, has also been simulated using Spectre and BSIM3V3 device models for 1.8V 180nm CMOS technology from UMC. Most important simulation results are presented. |
Year | Venue | Keywords |
|---|---|---|
2013 | MIXDES | cmos analogue integrated circuits,delay lines,delay lock loops,trigger circuits,bsim3v3 device models,cmos technology,dcc,dll,spectre device models,analog dual delay locked loop,coarse delay segment,coarse programmable delay elements,duty cycle correction,fine programmable delay elements,fine programmable delay line,simply-implementable coarse delay line,single-ended schmitt triggers,size 180 nm,variable-delay elements,voltage 1.8 v,schmitt trigger,analog variable-delay elements,current starved inverter,delay line architectures,synchronization,detectors |
Field | DocType | ISBN |
Delay calculation,Delay line oscillator,Lock (computer science),Computer science,Duty cycle,Delay-locked loop,CMOS,Electronic engineering,Digital delay line | Conference | 978-83-63578-00-8 |
Citations | PageRank | References |
6 | 0.74 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jasielski, J. | 1 | 6 | 0.74 |
| S. Kuta | 2 | 7 | 2.18 |
| Witold Machowski | 3 | 8 | 2.87 |
| Wojciech Kolodziejski | 4 | 7 | 1.85 |