Paper Info
Title
A reconfigurable computing architecture using magnetic tunneling junction memories
Abstract
This work presents a new dynamically reconfigurable architecture that uses magnetic tunneling junctions to implement non-volatile reconfiguration memories. The magnetic-based storage elements further provide a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional array of double precision floating-point run-time reconfigurable execution units. The configuration information defines the operation to be executed and the data flow intra and inter execution units. A prototype design of the coarse-grained reconfigurable array has been implemented targeting a 65nm CMOS technology. The obtained results confirm that the proposed architecture provides a significant computational density and that the magnetic memories provide a very area efficient multi-context based run-time reconfigurability.
Year
DOI
Venue
2013
10.1109/FPL.2013.6645616
Field Programmable Logic and Applications
Keywords
Field
DocType
CMOS memory circuits,magnetic tunnelling,memory architecture,random-access storage,reconfigurable architectures,2-dimensional array,CMOS technology,configuration information,double precision floating-point run-time reconfigurable execution units,magnetic memories,magnetic tunneling junction memories,magnetic-based storage elements,multicontext planes,multicontext-based run-time reconfigurability,nonvolatile reconfiguration memories,prototype design,reconfigurable array,reconfigurable computing architecture,size 65 nm
Quantum tunnelling,Architecture,Reconfigurability,Computer science,Parallel computing,Double-precision floating-point format,CMOS,Memory architecture,Control reconfiguration,Data flow diagram
Conference
ISSN
Citations 
PageRank 
1946-1488
1
0.36
References 
Authors
5
4
Name
Order
Citations
PageRank
Victor Silva152.24
Jorge R. Fernandes215434.16
Mario P. Vestias361.63
Horácio C. Neto417224.25