Name
Title | ||
|---|---|---|
A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications |
Abstract | ||
|---|---|---|
An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based counterpart shows a jitter performance of 195 fs (rms). The PLL occupies 0.093 mm2 and consumes 15.5 mA at 1.0V. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/CICC.2013.6658471 | Custom Integrated Circuits Conference |
Keywords | Field | DocType |
CMOS digital integrated circuits,active filters,capacitors,integrated circuit noise,jitter,mean square error methods,multiplying circuits,passive filters,phase locked loops,PLL performance,RMS jitter,analog PLL,capacitor multiplier loop filter-based PLL,capacitor multiplier-based active loop filter,current 15.5 mA,digital CMOS process,digital PLL,frequency 8 GHz to 12.2 GHz,high-speed serial communication applications,jitter performance,passive loop filter-based version,size 28 nm,voltage 1 V | Serial communication,Phase-locked loop,Capacitor,Active filter,Computer science,PLL multibit,Electronic engineering,Multiplier (economics),CMOS,Control engineering,Jitter | Conference |
Citations | PageRank | References |
4 | 0.53 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Catli, B. | 1 | 4 | 0.53 |
| Nazemi, A. | 2 | 4 | 0.53 |
| Ali, T. | 3 | 4 | 0.53 |
| Fallahi, S. | 4 | 17 | 1.46 |