Name
Abstract | ||
|---|---|---|
Although individual stages of current graphics processing units (GPU) are programmable via shaders, the pipeline still contains fixed blocks and the data flow cannot be adjusted arbitrary. To overcome these limitations, we propose a novel graphics processor architecture, which substantially improves reconfigurability of the rendering pipeline. For this purpose, we model the complete rendering pipeline as a functional program, which is then represented as a stream of tokens and iteratively modified by a set of rewriting rules. Our proposed architecture enables dynamic thread creation, lock-free synchronization and light-weight scheduling based on pattern matching. Reconfigurability and scalability of the novel processor architecture are demonstrated by complex examples running on an FPGA prototype. |
Year | Venue | Keywords |
|---|---|---|
2013 | Design and Architectures for Signal and Image Processing | field programmable gate arrays,graphics processing units,pattern matching,rendering (computer graphics),scheduling,synchronisation,FPGA prototype,GPU,dynamic thread creation,field programmable gate array,functional program,graphics processing units,graphics processor architecture,light-weight scheduling,lock-free synchronization,partial stream rewriting,pattern matching,processor architecture reconfigurability,processor architecture scalability,rendering pipeline reconfigurability,rewriting rules |
Field | DocType | Citations |
Graphics pipeline,Computer science,Alternate frame rendering,Parallel computing,Real-time computing,Real-time computer graphics,General-purpose computing on graphics processing units,Rendering (computer graphics),Software rendering,Shader,Tiled rendering | Conference | 0 |
PageRank | References | Authors |
0.34 | 16 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lars Middendorf | 1 | 16 | 4.07 |
| Christian Haubelt | 2 | 796 | 68.77 |