Name
Abstract | ||
|---|---|---|
Embedded systems increasingly need to support dynamic and diverse application landscape. In response, performance asymmetric multi-cores, comprising of identical instruction-set architecture but micro-architecturally distinct set of simple and complex cores, have emerged as an attractive alternative to accommodate software diversity. Dynamic heterogeneous multi-core architectures take this concept forward by allowing on-demand formation of virtual asymmetric multi-cores through coalition of physically symmetric simple cores and thus adjust better to workload variation at runtime. In this paper, we present the first hardware implementation of a core coalition architecture and synthesize its functional prototype on FPGAs. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLSI-SoC.2013.6673275 | Very Large Scale Integration |
Keywords | Field | DocType |
field programmable gate arrays,instruction sets,FPGA,core coalition architecture,dynamic application,dynamic heterogeneous multicore architectures,embedded systems,identical instruction set architecture,microarchitecturally-distinct set,on-demand formation,performance asymmetric multicores,physically-symmetric cores,software diversity,virtual asymmetric multicores,workload variation | Architecture,Computer architecture,Workload,Instruction set,Computer science,Field-programmable gate array,Software diversity,Embedded system | Conference |
Citations | PageRank | References |
0 | 0.34 | 12 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaushik Triyambaka Mysur | 1 | 0 | 0.34 |
| Mihai Pricopi | 2 | 17 | 0.99 |
| Thomas Marconi | 3 | 0 | 0.34 |
| Tulika Mitra | 4 | 2714 | 135.99 |