Paper Info
Title
Improved read voltage margins with alternative topologies for memristor-based crossbar memories
Abstract
Memories based on hysteretic resistive materials are expected to have superior properties such as nonvolatility, low power consumption, as well as very high capacity. Crossbar arrays are considered very attractive for future ultimately scaled memories. In this paper, the memristor-based passive crossbar geometry is studied and a set of different topological patterns, which introduce insulating junctions within the memory array, is presented. In the worst-case reading scenario the simulations revealed significantly improved sensed voltage margins (up to > 4×) which alleviate the rigorous requirement for large and highperformance CMOS sensing circuits in passive crossbar memory systems.
Year
DOI
Venue
2013
10.1109/VLSI-SoC.2013.6673304
Very Large Scale Integration
Keywords
Field
DocType
CMOS integrated circuits,low-power electronics,memristors,network topology,CMOS sensing circuits,alternative topologies,crossbar arrays,hysteretic resistive materials,low power consumption,memory array,memristor-based crossbar memories,memristor-based passive crossbar geometry,nonvolatility,read voltage margins,scaled memories,sensed voltage margins,worst-case reading scenario,crossbar,memory,memristor,nano-scale circuits,resistive random access memory
Memristor,Resistive touchscreen,Voltage,CMOS,Electronic engineering,Engineering,Electronic circuit,Crossbar switch,Low-power electronics,Resistive random-access memory
Conference
Citations 
PageRank 
References 
7
1.21
1
Authors
3
Name
Order
Citations
PageRank
Ioannis Vourkas19916.26
Dimitrios Stathis2244.20
Sirakoulis, G.C.31149.55