Name
Abstract | ||
|---|---|---|
Ongoing research to shrink feature sizes of LSI circuits leads to an always increasing number of logic gates in a circuit. In general, the complexity of test generation depends on the size of a circuit. Furthermore, modern test generation methods have to consider power reduction in addition to fault detection, since excessive power caused by testing may result in over testing. In this work, we propose a method to reduce the computation time of low-power test generation. The proposed method specifies gates which will cause power issues, consequently reducing the search space for X-filling technique. The reduction of search space for Xfilling also further minimizes the amount of switching activity. Experimental results for circuits of Open Cores provided by IWLS2005 benchmarks show that the proposed method achieves both a reduced computation time and at the same time increased power reduction compared to previous methods. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ATS.2013.40 | Asian Test Symposium |
Keywords | Field | DocType |
automatic test pattern generation,large scale integration,logic circuits,logic gates,logic testing,low-power electronics,IWLS2005 benchmarks,LSI circuits,X-filling technique,fault detection,logic gates,low-power test generation,power reduction,search space reducing,search space reduction,X-filling,low-power testing,test generation | Automatic test pattern generation,Digital electronics,Sequential logic,Pass transistor logic,Logic optimization,Computer science,Electronic engineering,Logic family,Test compression,Low-power electronics | Conference |
ISSN | Citations | PageRank |
1081-7735 | 3 | 0.42 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. Miyase | 1 | 116 | 6.12 |
| Matthias Sauer | 2 | 195 | 20.02 |
| B. Becker | 3 | 191 | 21.44 |
| Wenyao Xu | 4 | 615 | 77.06 |