Name
Abstract | ||
|---|---|---|
An efficient implementation of a time-domain speech synthesis system on an ultra low-power, miniature, programmable block- floating-point DSP system is introduced. The DSP system, operating at a clock rate as low as 1.28 MHz, is well suited for speech and audio processing applications. Similar to the MBR- PSOLA technique, this time-domain synthesis method uses a normalized speech database generated by a high-quality harmonic synthesis. To reduce the memory usage and communication bandwidth, the normalized database is compressed using a block-adaptive, ADPCM approach. Listening tests comparing the synthetic speech quality on the DSP system and the same method implemented on a high-resource computer system show no degradations due to the memory, register length, or other low-resource limitations on the DSP system. The system consumes less than 1 mW at 1 volt. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ICASSP.2002.5743747 | ICASSP), 2002 IEEE International Conference |
Keywords | Field | DocType |
hardware,harmonic analysis,speech synthesis,databases,time domain,real time | Speech synthesis,Digital signal processing,Computer science,Speech quality,Harmonic,Harmonic analysis,Communication bandwidth,Audio signal processing,Computer hardware,Clock rate | Conference |
Volume | ISSN | ISBN |
1 | 1520-6149 | 0-7803-7402-9 |
Citations | PageRank | References |
2 | 0.39 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hamid Sheikhzadeh | 1 | 2 | 0.39 |
| Etienne Cornu | 2 | 20 | 4.81 |
| Robert Brennan | 3 | 5 | 1.83 |
| Todd Schneider | 4 | 34 | 6.22 |