Name
Abstract | ||
|---|---|---|
Summary form only given. The energy efficiency of electronic circuits has dramatically improved over the past two decades. At the same time, computation, storage, and communication demands continue to grow with emerging wireless multimedia devices. In this inaugural Plenary Technology-Roundtable event, experts will discuss the opportunities to achieve the next order-of-magnitude reduction in energy consumption across various domains, including analog, digital, RF, and memory. The line between analog and digital continues to blur, as analog circuits are enhanced by applying digital corrections to compensate for increased analog component variability with process scaling. As well, digital will incorporate more analog to become more adaptive; for example, to optimize operating voltages at a fine-grain to match workloads and process variations. Memory circuits will need to use a system-level approach which requires bit-cell optimization, low-voltage operation with integrated regulators, 3D Through-Silicon Vias (TSV), and process optimization. RF transceivers will continue to trend toward highly-digital architectures. The role of process-technology innovation and CAD tools will also be discussed. Future process technology will deliver new transistor structures and higher-mobility channel materials for low-voltage digital circuits. TSVs will be important in reducing I/O power and the length of on-chip interconnects. For RF, integrated inductors and transformers with significantly lower resistance will be the challenge. Future CAD tools optimizing energy will focus on co-design of packaging, architecture, power sources, and antenna to provide the best system solution. Domain experts will challenge the distinguished panelists to suggest directions and help create a roadmap for next-generation energy-efficient electronics. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746206 | Solid-State Circuits Conference Digest of Technical Papers |
Keywords | Field | DocType |
analogue circuits,digital circuits,3D through silicon vias,CAD tool,RF transceiver,analog circuit,analog component variability,bit cell optimization,digital correction,electronic circuit,energy consumption,energy efficiency,highly digital architecture,inaugural plenary technology-roundtable event,integrated inductor,integrated regulator,low voltage digital circuit,memory circuit,mobility channel material,next generation energy-efficient electronics,on-chip interconnect,order-of-magnitude reduction,process optimization,process scaling,process technology innovation,process variation,transistor structure,wireless multimedia device | Digital electronics,System on a chip,Analogue electronics,Computer science,Electronic engineering,Memory management,Electronics,Electronic design automation,Process variation,Energy consumption,Electrical engineering | Conference |
ISSN | ISBN | Citations |
0193-6530 | 978-1-61284-303-2 | 2 |
PageRank | References | Authors |
0.43 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jan M. Rabaey | 1 | 4796 | 1049.96 |
| DeMan, H. | 2 | 2 | 0.43 |
| Mark Horowitz | 3 | 6374 | 1543.34 |
| Takayasu Sakurai | 4 | 1039 | 280.69 |